With the mounting need for higher functionality and further miniaturization of electronic equipment, advances in integration technology of LSI and in size reduction of components, and changes in the mounting mode, the demand for high-density wiring is getting greater in the field of printed circuit boards and, as a consequence, development of the so-called multilayer circuit boards comprising 3 or more conductor layers has been broadly undertaken.
In view of the demand for higher wiring density in multilayer circuit boards, the so-called buildup multilayer circuit board is attracting attention. The buildup multilayer circuit board is manufactured by the technology disclosed in Japanese Kokai Publication Hei-4-55555, for instance. Thus, a core substrate board formed with a lower-layer conductor circuit is coated with an electroless plating adhesive comprising a photosensitive resin and, after the coat is dried, exposure to light and development are carried out to provide an interlayer resin insulating layer having openings for via holes. Then, the surface of this interlayer resin insulating layer is roughened with an oxidizing agent or the like and a thin electroless plated copper layer is formed on said interlayer resin insulating layer. Then, a plating resist is disposed thereon and a thick electroplated copper layer is constructed. The plating resist is then stripped off and the thin electroless plated copper layer is etched off to provide a conductor circuit pattern including via holes. This procedure is repeated a plurality of times to provide a multilayer printed circuit board.
When, in the above process for fabricating a printed circuit board, the direct-current plating (DC plating) method, which is one of the conventional electroplating techniques, is used to provide said electroplated copper layer on a substrate surface, the current generally tends to be concentrated in the marginal area of the substrate surface as compared with the central area so that, as illustrated in FIG. 6, the thickness t12 of the copper layer in the marginal area of the substrate surface tends to become greater than the thickness t11 in the central area, thus causing a regional variation in thickness of the electroplated copper layer.
Since, in actual production runs, said substrate surface is the surface of a substrate board (work size substrate) having a large area corresponding to a large number of printed circuit boards integrated (specifically, the average one has an area of 255 to 510 mm square and there is even one having an area of about 1020 mm square at a maximum), the above tendency is particularly pronounced.
In the manufacture of printed circuit boards, when the electroplated copper layer constituting a conductor circuit is not uniform in thickness, the insulation interval t14 between conductor layers in the marginal region of the substrate board is relatively smaller than the insulation interval t13 between conductor layers in the central region of the substrate board as shown in FIG. 7, so that the thickness of the insulating layer 1101b between conductor layers must be increased in order to insure a sufficient insulation in all regions of the printed circuit board but this is a hindrance to the implementation of high-density wiring.
In addition, when the copper layer is formed by direct current plating, the crystallinity of the plated copper is low because of the use of an organic additive for improved throwing power. Moreover, the residual stress in the plated copper layer is fairly large so that the layer tends to develop cracks and other flaws and show low elongation and high tensile strength characteristics. Therefore, an annealing step for reducing the residual stress has been essential to the manufacture of printed circuit boards.
As a technology for insuring the uniformity of thickness of the plated copper layer, it has been proposed to form a thick plated copper layer by electroless plating alone without electroplating. However, the thick plated copper layer formed by electroless plating is poor in ductility because of the unavoidable contamination of the layer with many impurities inclusive of the additives used. Therefore, when a thick plated copper layer is formed by electroless plating, the reliability for the wiring and connection is insufficient and in order to attain a sufficient degree of reliability, an annealing step is indispensable in this case, too.
To overcome the above problem, a technology for constructing a thick plated copper layer by a constant-current pulse electrolytic technique has been proposed.
The constant-current pulse electroplating process is characterized in that the plating current is controlled at a constant level and the representative waveform involved is a square wave.
This technology may be further divided into the process (PC plating process; FIG. 8) in which the current is controlled by means of the square pulse wave available by repetition of the alternating supply (ON) and interruption (OFF) of the cathode current and the pulse-reverse electroplating method (PR plating method; FIG. 9) in which the current is controlled with a periodically reversed wave available by repetition of the alternating supply of cathode current and supply of anode current. As compared with the direct current electroplating process, the non-steady diffusion layer can be reduced in thickness in either process, with the result that a smooth plated metal layer can be constructed and further that since plating can be effected at a high pulse current density (high overvoltage), the evolution of crystal seeds is promoted to yield finer crystal grains, thus enabling formation of a plated metal layer of high crystallinity. As an example of the PR electroplating method, the process disclosed by Fujinami et al. (Surface Technology, “Formation of Via Filling by PR Electrolysis”, 48 [6], 1997, p. 86–87).
However, when the plated copper layer is formed by PC process, the uniformity of layer thickness is superior to that obtainable by direct current plating process but is not as good as the objective level (FIG. 4).
On the other hand, the plated copper layer formed by PR process is improved in the uniformity of thickness as compared with the layer obtainable by PC process but is not as high as desired yet and, moreover, plating by PR process requires an expensive current source.
The current mainstream of electroless plating in the manufacture of printed circuit boards uses EDTA as a complexing agent, and examples of formation of copper circuits with such electroless plating solutions can be found in the Best Mode sections of Japanese Kokai Publication Sho-63-158156 and Japanese Kokai Publication Hei-2-188992 (corresponding to U.S. Pat. No. 5,055,321 and U.S. Pat. No. 5,519,177).
However, with a plating solution containing EDTA as a complexing agent, a compressive stress (an expanding force) is generated in the plating metal layer to cause peeling of the plated copper film from the resin insulating layer.
Furthermore, there is also found the problem not to deposit within fine via holes not over 80 μm in diameter.
Moreover, in the conventional processes for manufacture of printed circuit boards, it was impossible to construct fine-definition line conductor circuits on core boards. Thus, the prior art method for forming a conductor circuit on the core substrate board for a printed circuit board is now described with reference to FIG. 27. As the core substrate board, a copper-clad laminate 3330A comprising a resin substrate 3330 and, as clad to both sides thereof, a copper foil 3331 (FIG. 27 (A)) is used. First, through holes 3332 are drilled in this core board (FIG. 27 (B)). Then, a plating metal is uniformly deposited (3333) to form plated-through holes 3336 in said holes 3332 (FIG. 27 (C)). Then, the copper foil 3331 formed with the plated metal layer 3333 is subjected to pattern-etching to provide a conductor circuit 3334 (FIG. 27 (D)). After an interlayer resin insulating layer 3350 is formed over said conductor circuit 3134, plating is performed to provide a conductor circuit 3358 (FIG. 27 (E)).
In the above process according to the conventional technology, the thickness of copper foil 3331 is at least 18 μm and the thickness of the plated metal layer formed thereon is 15 μm. Since the combined thickness is as large as 33 μm, etching produces undercuts on the lateral sides of the conductor 3334 as shown in FIG. 27 (D) and since the circuit layer then is liable to peel off, it has been impossible to construct a fine-line conductor circuit.
Furthermore, the conductor circuit 3358 on the interlayer resin insulating layer 3350, shown in FIG. 27 (E), has been formed in a thickness of about 15 μm. In contrast, the conductor circuit 3334 on the core board 3330 has a thickness of 33 μm. This means that a large impedance difference is inevitable between the conductor circuit 3358 on the interlayer resin insulating layer 3350 and the conductor circuit 3334 on the core board and because of difficulties in impedance alignment, the high-frequency characteristic of the circuit board cannot be improved.
Moreover, in the above process for fabricating a printed circuit board, when the substrate surface is copper-plated by direct-current (DC) electroplating which is general electroplating technique, the plating metal is deposited in the same thickness over the via hole openings and the conductor circuit-forming area.
This results in formation of depressions in the areas of the interlayer resin insulating layer which correspond to the via holes. Another problem is that the structure called “stacked via”, namely formation of a via hole over a via hole, cannot be constructed.
In addition, for the following reasons, the conventional printed circuit board has the drawback that its size and thickness are increased beyond what are required. Thus, as shown in FIG. 38 (A), the printed circuit board 5210 for use as a package board for mounting the IC chip 5290 is fabricated by building up interlayer resin insulating layers 5250, 5350 and conductor layers 5258, 5358 in an alternating manner on a core board 5230 formed with plated-through holes 5236 and disposing bumps 5276U for connection to the IC chip 5290 on the top surface and bumps 5276D for connection to a mother board on the bottom side. The electrical connection between the top and bottom conductor layers is afforded by via holes 5260, 5360. While the via holes 5260 are adjacent to the IC chip 5290 of the core board 5230, the via holes 5360 adjacent to the mother board. These via holes are connected to each other through the corresponding plated-through holes 5236. Thus, on the face side of the core board 5230 of this printed circuit board 5210, as shown in FIG. 38 (B) which is a sectional view taken along the line B—B of FIG. 38 (A), the land 5236a of the plated-through hole 5236 is provided with an inner layer pad 5236b for via-hole connection to the upper layer, while the via hole 5260 is connected to this inner layer pad 5236b. 
However, with the prior art land configuration illustrated in FIG. 38 (B), the interval between plated-through holes must be large enough to insure a mutual insulation of inner layer pads 5236b, thus restricting the number of plated-through holes that can be constructed in the core board.
On the other hand, the package board is formed with a larger number of bumps on the face side than on the reverse side. This is because the wirings from the plurality of bumps on the surface are consolidated and connected to the bumps on the reverse side. For example, the power lines required to be of low resistance compared with signal lines, which number 20, for instance, on the face side (IC chip side) are consolidated into a single line on the reverse side (on mother board side).
Here, it is preferable that the buildup circuit layer formed on the face side of a core board and the buildup circuit layer on the reverse side may be consolidated at the same pace for the purpose of equalizing the number of upper buildup circuit layers to the number of lower buildup circuit layers, that is to say for minimizing the number of layers. However, as mentioned above, there is a physical restriction to the number of plated-through holes which can be formed in a multilayer core board. Therefore, in the prior art package board, the wirings are consolidated to some extent in the buildup circuit layer on the face side and then connected to the buildup circuit layer on the reverse side through the plated-through holes in the multilayer core board. Since the wiring density has thus been decreased in the buildup circuit layer on the reverse side, it is intrinsically unnecessary to provide the same number of layers on the reverse side as in the buildup circuit layers on the face side. However, the same number of layers has heretofore been used because if there is a difference in the number of layers between the face and reverse sides, warping due to asymmetry would be inevitable. Thus, because of said restriction to the number of plated-through holes which can be provided in the multilayer core board, it is not only necessary to increase the number of layers for the buildup wiring layer on the face side but also necessary to form the buildup circuit layer on the reverse side using the same increased number of layers on the face side.
Thus, in the prior art multilayered buildup circuit board (package board), the number of built-up layers is increased so that the reliability of connection between the upper and lower layers is low. Moreover, the cost of the package board is increased and the size, thickness and weight of the package board are unnecessarily increased.
Furthermore, even when the buildup multilayer circuit board is provided only on one side of a core board, provision must be made for a freedom in wiring design for the side opposite to the side formed with the buildup layer.
Moreover, since the connection between plated-through hole 5236 and via hole 5260 is afforded through an inner layer pad 5236b as described above, the wiring length within the printed circuit board is increased to sacrifice the signal transmission speed, thus making it difficult to meet the demand for speed-up of IC chips.